This invention relates to a single plane, programmable logic array (PLA) using dynamic CMOS logic and more particularly to the implementation of such a PLA as a multiplexer.
The PLA has emerged as an important building block in many VLSI circuit designs, particularly in microprocessors and digital signal processors. The highly regular structure of PLAs greatly simplifies the automated design and layout of complex logic circuits and permits a large reduction in the silicon area required for a given function. Typically PLAs decrease design complexity and silicon area but degrade power and speed performance relative to custom logic.
A standard PLA consists of two matrices: the AND plane and the OR plane. In each matrix, according to the presence or absence of switching transistors at matrix cross-points, a certain combination of inputs on a set of row (or column) lines gives a certain combination of outputs respectively on the column (or row) lines. The outputs of the AND plane are called products and the outputs of the OR plane are called sums. According to Boolean algebra, any logic equation can be reduced to the sum of products. Therefore a single PLA can be used to implement any combinational logic equation by having the outputs of the AND plane form the inputs to the OR plane. "Combinational" means that the output is a function of a combination of present inputs and is not dependent on previous inputs or outputs, i.e. the PLA has no memory.
Essentially there are two ways of implementing the core of a logic plane: logic inputs are connected to the gates of Transistors and the transistors are connected either in series (NAND) or in parallel (NOR). The "series" version requires less area but the "parallel" version is faster. Usually the same structure is used in both planes of the PLA to maximize speed or density. The two versions are equivalent since two NOR planes are equivalent to an AND plane followed by an OR plane when the inputs and outputs are inverted.
The PLA structure may be dynamic or static in operation. Since power density is an important consideration in VLSI totally dynamic PLAs are attractive. Dynamic operation permits a denser logic array since minimum transistor sizes can be used throughout. The resulting smaller gate capacitances further improve the power reduction achieved by eliminating pull-up transistors characteristic of static PLAs. This approach is particularly suited to NMOS technology. Unfortunately the use of two or more possibly non-overlapping clock phases decreases the maximum frequency of operation and increases circuit complexity.
Co-pending U.S. Pat. application No. 440,870, now abandoned, describes a simple high speed PLA structure implemented in a standard CMOS process. The basic structure used in each plane of the PLA is a NOR gate. The PLA described in that patent specification is highly regular and thus simplifies automated design and layout of complex logic circuits and, in addition, provides savings in silicon area. Frequently the activated part of the OR plane, i.e. the number of transistors at matrix cross-points as a percentage of the total number of cross-points is quite low. In such a case the area of silicon is not used to its highest efficiency.
The PLA area can be reduced by dispensing altogether with the OR plane and having the AND plane perform the OR plane functions. This renders the AND plane slightly more complex, but especially if the required combinational logic capabilities of the PLA are somewhat limited, the overall saving in silicon area is well worthwhile.